The present invention relates to a semiconductor memory device including a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate.
Recently, ferroelectric random-access memories (which will be herein referred to as “FeRAMs”) for use in IC cards or portable electronic units have been developed by semiconductor manufacturers. FeRAMs are nonvolatile memories, i.e., some contents stored thereon are not lost even when power is removed, and yet can operate almost as fast as DRAMs.
Most of the FeRAMs currently under development have either a two-transistor two-capacitor (2T2C) memory cell structure or a one-transistor one-capacitor (1T1C) memory cell structure. Therefore, in order to downsize FeRAMs, advanced patterning technology, including a technique of realizing a stereoscopic capacitor structure, is required. The difficulty in downsizing a memory is a common problem for both FeRAMs and DRAMs alike, and should constitute a serious obstacle to further increasing the density or capacity of a memory in the near future.
Meanwhile, as another circuit configuration for FeRAMs, a ferroelectric FET memory (which will be herein referred to as an “FeFET memory”) comprising a field-effect transistor, in which part of the gate insulating layer is a ferroelectric layer, has also been under research and development. Since the FeFET memory includes no capacitors, it is possible to avoid the downsizing problem. In other words, the FeFET memory can not only be a nonvolatile, high-speed-operating memory just like the known FeRAM but also realizes high density. Thus, the memory is considered to have ultimate characteristics for a semiconductor memory.
A cell structure for a known semiconductor memory device, specifically, a cell structure for an FeFET memory, will be described with reference to FIG. 5.
As shown in FIG. 5, insulating layer 104, floating gate 105, ferroelectric layer 106 and gate electrode 107 are stacked in this order on a semiconductor substrate 101 in which a source region 102 and a drain region 103 are defined. In this case, the floating gate 105 and the gate electrode 107 are usually made of metal(s), and the FeFET memory structure shown in FIG. 5 is called an “MFMIS structure”, in which MFMIS is the acronym for Metal (gate electrode 107), Ferroelectric (ferroelectric layer 106), Metal (floating gate 105), Insulator (insulating layer 104) and Semiconductor (semiconductor substrate 101).
As for a memory cell with the structure shown in FIG. 5, the voltage applied to the gate electrode 107 (which will be herein referred to as a “gate voltage”) generates a potential difference between both ends of the ferroelectric layer 106, thus producing polarization in the ferroelectric layer 106. The conductance between the source region 102 and the drain region 103 changes depending on whether the direction of the polarization is upward (toward the gate electrode 107) or downward (toward the semiconductor substrate 101). Thus, even when a gate voltage of the same level is applied to the gate electrode 107, different amounts of currents flow between the source region 102 and the drain region 103, thus realizing a memory function.
Furthermore, since the ferroelectric layer 106 retains the same polarization direction even when the gate voltage applied is removed from the layer, the memory function includes a nonvolatile characteristic as well.
In the known FeFET memory cell structure, however, even when the gate voltage is removed, a potential generates in the floating gate 105 due to the existence of the polarization in the ferroelectric layer 106. Thus, a leakage current flows from the floating gate 105 into the semiconductor substrate 101 and the gate electrode 107 through the insulating layer 104 and the ferroelectric layer 106 respectively, resulting in non-negligible decrease of effective charges stored in the floating gate 105.
In this case, when silicon dioxide is used for a material for the insulating layer 104, the amount of leakage current flowing though the insulating layer 104 substantially stays within a negligible range, compared to that of the leakage current flowing through the ferroelectric layer 106. However, it is difficult to realize a good leakage current characteristic for the ferroelectric layer 106 in the present circumstances. Therefore, as for FeFET memory cells currently available, the memory retention characteristic (which will be herein referred to as a “retention characteristic”) is at most ten days mainly because of the leakage current flowing into the gate electrode 107 by way of the ferroelectric layer 106. That is to say, the 10 year retention characteristic, which is essential for commercial applications, has not been fulfilled yet.